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Data Path Bit Width
CLK
DATAI_VALID
READY
busy
busy
busy
DATAI
Valid data
Figure 40 · Data Source Is Always Ready
Output Rate Control
As the output sample rate of the Interpolation filter is higher than the data rate, there might be a need for a
slow downstream device to control the filter throughput. You can do this using the RCLK signal by
deasserting it for a number of clock cycles. The core expects the RCLK signal to be active for a full clock
cycle. If a recipient of the interpolated samples asserts the RCLK every other clock cycle, the sample rate
diminishes with a factor of two. The RCLK active every third clock cycle reduces the output sample speed by
three times, etc. The core automatically adjusts the READY signal for the data source to drop rate as well.
Figure 41 presents the case depicted on Figure 40 but the output sample rate equals one third of the
Figure 40 rate due to lowering the RCLK signal for two clock cycles out of every three. It is seen the READY
signal got slower, too.
CLK
RCLK
DATAI_VALID
READY
DATAI
Valid data
Figure 41 · RCLK Used to Reduce the Output Rate by Three Times
If the downstream device can handle interpolated samples at clock rate, the signal RCLK should be
connected to VCC or left unconnected.
CoreFIR v8.5 Handbook
45
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